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ARIZONA MICROTEK, INC.
AZP92
ECL/PECL /1, /2 Clock Generation Chip with Selectable Enable FEATURES
* * * * * * * * * PACKAGE AVAILABILITY
Green and RoHS Compliant / Lead (Pb) PACKAGE PART NO. MARKING NOTES Free Package Available MLP 8 (2x2) Green P1G 3.0V to 5.5V Operation / RoHS Compliant AZP92NAG 1,2 Selectable Divide Ratio / Lead (Pb) Free Selectable Enable Polarity and 1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Threshold (CMOS/TTL or PECL) Tape & Reel. 2 Date code format: "Y" for year followed by "WW" for week. Selectable Input Biasing High Bandwidth for 1GHz -147 dBc/Hz (/1), -150 dBc/Hz (/2) Typical Noise Floor Available in a MLP 8 (2x2) Package S Parameter and IBIS Model Files Available on Arizona Microtek Website
DESCRIPTION
The AZP92 is a specialized /1 or /2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a /2 divider. A selectable enable is provided which also functions as a reset when the /2 mode is selected. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20k resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75k pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75k pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20k resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal 75k pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). This default logic condition can be overridden by connecting the EN to VCC with an external resistor of 20k. Refer to the enable truth table on the next page for detailed operation. MLP 8, 2x2 mm Package (AZP92NA) The AZP92NA provides a VBB with an 1880 internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a 0.01 F capacitor. NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
1630 S. STAPLEY DR., SUITE 127 * MESA, ARIZONA 85204 * USA * (480) 962-5881 * FAX (623) 505-2414 www.azmicrotek.com
AZP92
SIGNAL DESCRIPTION PIN/PAD D Q/Q VBB/D EN EN-SEL DIV-SEL VEE VCC FUNCTION Data Input Data Outputs Reference Voltage Output Enable/Reset Input Enable Logic Select Divide Ratio Select Negative Supply Positive Supply
ENABLE TRUTH TABLE EN-SEL NC NC VEE VEE 20k to VEE 20k to VEE EN CMOS Low or VEE CMOS High, VCC or NC CMOS Low, VEE or NC CMOS High or VCC PECL Low, VEE or NC PECL High or VCC Q Low Data Low Data Data Low Q High Data High Data Data High
DIVIDE TRUTH TABLE DIVIDE RATIO NC /1 VEE1 /2 1 DIV-SEL connection must be 1. DIV-SEL
D EN (EN-SEL CONNECTED TO
VEE VIA 20k RESISTOR)
(PECL)
EN (EN-SEL OPEN OR
CONNECTED TO VEE)
(CMOS)
Q Q
(DIV-SEL OPEN) (DIV-SEL CONNECTED TO VEE)
TIMING DIAGRAM
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AZP92
AZP92NA MLP 8, 2x2 mm
TOP VIEW
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AZP92
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol VCC VI VEE VI IHGOUT TA TSTG Characteristic PECL Power Supply (VEE = 0V) PECL Input Voltage (VEE = 0V) ECL Power Supply (VCC = 0V) ECL Input Voltage (VCC = 0V) Output Current -- Continuous -- Surge Operating Temperature Range Storage Temperature Range Rating 0 to +6.0 0 to +6.0 -6.0 to 0 -6.0 to 0 50 100 -40 to +85 -65 to +150 Unit Vdc Vdc Vdc Vdc mA C C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1. 2. 3. 4. Characteristic
1
-40C Min -1085 -1900 Max -880 -1555 Min -1025 -1900
0C Max -880 -1620 -390 VCC -1475 VEE + 800 -1250 150 Min -1025 -1900
25C Max -880 -1620 -390 VCC -1475 VEE + 800 -1250 150 Min -1025 -1900
85C Max -880 -1620 -390 VCC -1475 VEE + 800 -1250 150
Unit mV mV mV mV mV A A
Output HIGH Voltage Output LOW Voltage1 Input HIGH Voltage -1165 -390 D/D, EN (ECL)2 -1165 VCC EN (CMOS)3 VEE+2000 VEE+2000 Input LOW Voltage -2250 -1475 -2250 D/D, EN (ECL)2 VEE VEE + 800 VEE EN (CMOS)3 Reference Voltage -1390 -1250 -1390 Input HIGH Current EN 150 Input LOW Current 0.5 0.5 EN (ECL)2 -150 -150 EN (CMOS)3 Power Supply Current4 31 Specified with outputs terminated through 50 resistors to VCC - 2V. EN-SEL connected to VEE through a 20k resistor. EN-SEL connected VEE or left open (NC). DIV-SEL left open (NC).
-1165 VEE+2000 -2250 VEE -1390
-1165 VEE+2000 -2250 VEE -1390
0.5 -150 31 31
0.5 -150 34
mA
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1. 2. 3. 4. 5. Characteristic
1,2
-40C Min 2215 1400 Max 2420 1745 Min 2275 1400
0C Max 2420 1680 Min 2275 1400 2135 2000 1050 GND 1910
25C Max 2420 1680 2910 VCC 1825 800 2050 150 Min 2275 1400 2135 2000 1050 GND 1910
85C Max 2420 1680 2910 VCC 1825 800 2050 150
Unit mV mV mV mV mV A A
Output HIGH Voltage Output LOW Voltage1,2 Input HIGH Voltage1 2135 2910 2135 2910 D/D, EN (PECL)3 EN (CMOS)4 2000 VCC 2000 VCC Input LOW Voltage1 1050 1825 1050 1825 D/D, EN (PECL)3 EN (CMOS)4 GND 800 GND 800 1 Reference Voltage 1910 2050 1910 2050 Input HIGH Current EN 150 150 Input LOW Current 0.5 0.5 EN (PECL)3 -150 -150 EN (CMOS)4 Power Supply Current5 31 31 For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value. Specified with outputs terminated through 50 resistors to VCC - 2V. EN-SEL connected to VEE through a 20k resistor. EN-SEL connected VEE or left open (NC). DIV-SEL left open (NC).
0.5 -150 31
0.5 -150 34
mA
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AZP92
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1. 2. 3. 4. 5. Characteristic
1,2
-40C Min 3915 3100 Max 4120 3445 Min 3975 3100
0C Max 4120 3380 Min 3975 3100 3835 2000 2750 GND 3610
25C Max 4120 3380 4610 VCC 3525 800 3750 150 Min 3975 3100 3835 2000 2750 GND 3610
85C Max 4120 3380 4610 VCC 3525 800 3750 150
Unit mV mV mV mV mV A A
Output HIGH Voltage Output LOW Voltage1,2 Input HIGH Voltage1 3835 4610 3835 4610 D/D, EN (PECL)3 EN (CMOS)4 2000 VCC 2000 VCC Input LOW Voltage1 2750 3525 2750 3525 D/D, EN (PECL)3 EN (CMOS)4 GND 800 GND 800 1 Reference Voltage 3610 3750 3610 3750 Input HIGH Current EN 150 150 Input LOW Current 0.5 0.5 EN (PECL)3 -150 -150 EN (CMOS)4 Power Supply Current5 31 31 For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. Specified with outputs terminated through 50 resistors to VCC - 2V. EN-SEL connected to VEE through a 20k resistor. EN-SEL connected VEE or left open (NC). DIV-SEL left open (NC).
0.5 -150 31
0.5 -150 34
mA
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Symbol tPLH / tPHL Characteristic Min -40C Typ Max Min 0C Typ Max Min 25C Typ Max 450 600 20 1000 2000 200 150 300 80 Min 85C Typ Max 450 600 20 1000 2000 200 Unit ps ps mV ps Propagation Delay 450 450 D to Q/Q Outputs1 (SE) 600 600 EN to Q/Q Outputs1 tSKEW Duty Cycle Skew2 (SE) 5 20 5 20 Input Swing3 150 1000 150 1000 150 VPP (AC) Differential (D/D) 300 2000 300 2000 300 Single Ended (D)4 Output Rise/Fall1 80 200 80 200 80 tr / t f (20% - 80%) 1. Specified with outputs terminated through 50 resistors to VCC - 2V. 2. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 3. The peak-to-peak input swing is the range for which AC parameters are guaranteed. 4. Range valid for AC coupled signals only.
5
5
AC PP INPUT (Differential)
D D V PP (AC)
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AZP92
Typical Large Signal Outputs, Q/Q
1000 900 800 700
VOUTpp(mV)
600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
Measured with 750mv D input, Q/Q each terminated to VCC-2V via 50 resistors.
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AZP92 PACKAGE DIAGRAM MLP 8 2x2mm
Pin 1 Dot By Marking 2.0000.050
2.0000.050
MLP 8 (2x2mm)
TOP VIEW
0.3500.050 0.2500.050 8 7 0.500 bsc 6 5 1
Pin 1 Identification R0.100 TYP
2 1.2000.050 exp. pad 3 4 0.6000.050 exp. pad
BOTTOM VIEW
1.750 Ref.
0.7500.050 0.000-0.050
1
2
34 0.2030.025
SIDE VIEW
Note: All dimensions are in mm
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AZP92
TAPE & REEL PACKAGING MLP 8 2x2mm
Direction of Travel
Package MLP 8 (2x2mm)
Suffix R1 R2
Reel Diameter 7" 13"
Quantity 1000 2500
Carrier Tape Width 8mm 8mm
Carrier Tape Pitch 4mm 4mm
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AZP92
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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